With the advent of sub-micron technology, integrated circuits (ICs) are becoming increasingly dense making them suitable for low power and low cost applications. Such ICs are typically tested using Automatic Test Pattern Generation (ATPG) tools, which simulate the overall functionality of an IC and generate test patterns, also referred to as test vectors. Various types of test patterns are provided for testing faults, such as, stuck-at faults, transition faults, and path-delay faults.
During testing, the number of test patterns and execution time of testing are tracked to minimize the overall cost of testing. The goal for any ATPG tool is to achieve the maximum test coverage with minimum number of test patterns. As a result, the nature of the test patterns may be such that the switching activity in the IC may be more than a specified power budget, for example, the switching activity may be 10% or more of the total possible switching per clock pulse. This can result in false failures and in some cases affect product reliability or cause permanent damage to the IC.
Controlling the switching activity during testing to stay within the specified power budget is desired for any low-power ATPG tool. Therefore, the low-power ATPG tools deterministically generate the test patterns to keep the switching activity below the specified power budget. For example, the ATPG tools target a limited number and limited types of faults such that the number of memory elements toggling, i.e. the switching activity, in response to a test pattern does not exceed the specified power budget.
The above mentioned methodology works well for ICs having a single clock domain or a plurality of clock domains whose clocks are derived from a single clock source. However, multiple clock domains, i.e., logic circuits operating at different clock frequencies, often exist within a single IC. The ATPG tools generally assign a combined power budget for all the clock domains. This translates into lesser flexibility in choosing the test patterns and reduced test coverage. Additionally, even though the ATPG tools may theoretically satisfy the power budget requirements for all the clock domains, the ATPG tools inaccurately report the switching activity for an individual clock domain.